1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory which receives a command and performs an internal operation.
2. Description of the Related Art
In general, when a command is inputted to a dynamic random access memory (DRAM) from a system chipset for controlling an operation of the DRAM, the DRAM and the system chipset may collide over command input timing due to asynchronous parameter values. For example, a command may not be inputted during its intended clock cycle, but may unintentionally be inputted during the next clock cycle.
In another example, when an interval between active commands inputted successively, that is, a RAS (row address strobe) to RAS delay (hereafter, referred to as tRRD) is set as 2tCK, and the interval between the active command and a corresponding column command (such as read and write commands), that is, a RAS to CAS (column address strobe) delay (hereafter, referred to as tRCD), is set as 4tCK, the column command and the read command may be inputted at the same time as the active command. In this case, however, since only one command may be inputted per clock cycle, the read command or the active command may be inputted at the next clock cycle resulting in internal operation being performed behind the proper timing.